1. Field of the Invention
The present disclosure relates generally to semiconductor memory devices and, more particularly, to electrically erasable and programmable semiconductor memory devices.
A claim of priority under 35 U.S.C. §119 is made to Korean Patent Application No. 2006-95908 filed on Sep. 29, 2006, the entire contents of which are hereby incorporated by reference.
2. Background of the Invention
Semiconductor memories are widely used in electronic components such as, for example, digital logic circuits and microprocessors. These and other such components may be used in a wide variety of applications ranging from satellite communications to consumer electronics. As demands such as reduction in size and increased operating speed in these applications increase, there is a corresponding demand for features such as high integration density and high frequency of operation from semiconductor devices. There is therefore a need to improve the technologies used in manufacturing semiconductor memories to fulfill such demands.
The semiconductor memory devices are generally classified into volatile memory devices and nonvolatile memory devices. In volatile semiconductor memory devices, information is stored on a temporary basis. This may be done in a number of ways. For example, in a volatile memory device, logical information may be stored by setting a logic condition of a bistable flipflop loop as in a static random access memory (SRAM) or by a capacitive charging effect as in a dynamic random access memory (DRAM.) Furthermore, the volatile semiconductor memory stores and reads data when powered on, but looses the stored data when power is cut off.
On the other hand, the nonvolatile semiconductor memories, such as, for example, MROM, PROM, EPROM, and EEPROM, are able to retain their data even when power supply is cut off. Furthermore, a storage condition in the nonvolatile memory may be designed to be either immutable or re-programmable in accordance with the fabrication techniques used to manufacture the semiconductor memory. Because of their ability, among other things, to retain data in the absence of power, nonvolatile semiconductor memory devices are used in a wide variety of applications. For example, nonvolatile memory devices are used for storing program files and micro-codes in applications such as, for example, computers, aerospace engineering, electronic engineering, communications, and customer electronics.
Among the nonvolatile semiconductor memories, MROM, PROM, and EPROM have features that may make it inconvenient for general users to reprogram these devices. The difficulty in reprogramming these devices lies in the design features of these devices which make it difficult to erase and write data to these devices. On the other hand, an EEPROM can be electrically erased and programmed with data. The ability to electrically erase and program an EEPROM memory makes the EEPROM memory widely popular with general users of electronic devices. Furthermore, flash EEPROMs (hereinafter, referred to as ‘flash memory devices’) can be fabricated with high integration density without compromising their ability to store large amounts of data. This feature makes flash EEPROMs popular as large-capacity auxiliary storage units.
A flash memory device generally includes an array of memory cells. Typically, each memory cell is formed of a floating gate transistor. Furthermore, the memory cell array is composed of a plurality of memory blocks. Each memory block, as shown in FIG. 1, includes strings, (referred even to as ‘NAND strings’ or ‘NAND unit’) each of which is formed of the floating gate transistors MCm˜MC0. In addition, the floating gate transistors are serially connected between a string selection transistor SST and a ground selection transistor GST, both of which are part of each string. Furthermore, the strings are electrically coupled to bit lines BL0˜BLn−1. Moreover, a plurality of word lines WL0˜WLm−1 are arranged such that they intersect with the NAND strings. Specifically, the plurality of word lines WL0˜WLm−1 are coupled to control gates of the floating gate transistors in the NAND strings.
Before floating gate transistors, i.e., memory cells, are programmed, the floating gate transistors are first erased to have negative threshold voltages (e.g., −1V or lower than 0V). This step may ensure that any data that was inadvertently present in the cell is removed before new data is programmed in the cell. While programming the memory cell, a high voltage is applied to a word line of a selected memory cell for a predetermined time. Upon application of this high voltage, the voltage level in the selected memory cell changes to have a higher threshold voltage, while the rest of the memory cells, i.e., deselected cells, maintain their threshold voltages without any changes to their voltage level.
However, applying a high threshold voltage to a word line including the memory cell to be programmed in the manner mentioned above may lead to problems. Specifically, the deselected memory cells that are connected to the word line including the selected cell may be inadvertently programmed when the high voltage is applied to the selected word line. This inadvertent programming of the deselected memory cells coupled to the selected word line is called ‘program disturbance’.
One technique for preventing program disturbance is program inhibition using a self-boosting scheme. In particular, methods of program inhibition with the self-boosting scheme are disclosed in U.S. Pat. No. 5,677,873 entitled ‘METHOD OF PROGRAMMING FLASH EEPROM INTEGRATED CIRCUIT MEMORY DEVICES TO PRE VENT INADVERTENT PROGRAMMING OF NONDESIGNATED NAND MEMORY CELLS THEREIN’, and U.S. Pat. No. 5,991,202 entitled ‘METHOD FOR REDUCING PROGRAM DISTURB DURING SELF-BOOSTING IN A NAND FLASH MEMORY’, both of which are incorporated by reference in this application.
In general, in a method of program inhibition using such a self-boosting scheme, a current path toward a ground voltage is interrupted by applying a voltage of 0V to a gate of the ground selection transistor GST. That is, the voltage of 0V is applied to the ground selection line GSL. In addition, a selected bit line is supplied with 0V as a program voltage while a deselected bit line is supplied with a power source voltage (Vcc) as a program-inhibition voltage. Particularly, the power source voltage is applied to a gate of the string selection transistor SST, i.e., to the string selection line SSL, and a pass voltage (Vpass) is applied to all of the word lines. This bias condition of voltages makes the string selection transistor SST shut off after charging a source of the string selection transistor SST up to Vcc-Vth (Vth is a threshold voltage of the string selection transistor). During this process, a channel voltage of a program-inhibited memory cell is boosted up, which prevents the F-N tunneling effect between its floating gate and channel. As a result, the program-inhibited cell transistor is maintained in its initial erased state. Thus, when the program voltage Vpgm is applied to the selected word line, only a selected memory cell is programmed by the F-N tunneling effect.
Ideally, as shown in FIG. 2, a voltage of the string selection line SSL would be at a target voltage when the pass voltage Vpass is applied to the word lines. However, in most cases, the voltage of the string selection line SSL may be boosted up by a coupling effect with its adjacent word line when the pass voltage Vpass is applied to the word lines. In many cases, the shut-off string selection transistor SST is turned on when the voltage of the string selection line SSL is boosted over the target voltage. Furthermore, the string selection transistor SST may remain in the on state for a limited period of time. This is because, after some time, the boosted voltage of the string selection line SSL returns to the target voltage.
The time during which the boosted voltage of the string selection line SSL recovers to the target voltage (hereinafter, referred to as ‘stabilizing time’) normally depends on a pattern of RC loading on the string selection line SSL. Specifically, such a stabilizing time may be directly proportional to the RC loading. Furthermore, because of the unwanted boosting of the SSL voltage and the subsequent time taken for the boosted voltage to return to the target value (shown by Dt1 in FIG. 2), the application of the program voltage Vpgm to the selected word line is delayed. Moreover, because of this delay in applying the program voltage Vpgm to the selected word line, an overall programming time may increase. This problem would be exacerbated in a multi-bit flash memory device that requires many more program loops than a single-bit flash memory device. Furthermore, when the shut-off string selection transistor SST is turned on by the boosted voltage of the string selection line SSL, a channel voltage of the program-inhibited memory cell may be lowered. This reduction of the channel voltage causes the program disturbance aforementioned, thus decreasing a window margin of the pass voltage. In addition, the aforementioned problems would be more serious due to signal skew on the string selection line SSL. Signal skew occurs because of the difference in the distances between different SSTs on the SSL from a row decoder.
The present disclosure is directed towards overcoming one or more of the shortcomings listed above in conventional flash memory programming operations.